This application claims priority based on provisional patent No. 60/397,491 filed on Jul. 22, 2002 by the applicant of the present invention.
The computer industry, with the advances of silicon technology, is constantly faced with the complexities of high speed Data Buses. The high speed of microprocessor CPU requires high speed of data bus between the memory subsystem and the front end CPU data bus. However, speed without density of memory is an unbalanced combination. Modern computer systems require increasingly large RAM arrays, and these arrays are packaged in modules of approximately the same size as used in previous, lower capacity memories. Thus, the density of the memory modules, in bits or bytes per square inch of circuit board, is constantly increasing.
The CPU by itself cannot increase computer performance without a high speed memory sub-system and it does not perform at the speed it was designed for. When memory access is substantially slower than CPU speed a bottleneck is created between memory and CPU Front End bus. With advances of the Internet, complex application programs and operating systems, memory sub-systems with high-density memory modules have become a necessity.
However, as the density of memory goes up, the capacitive loading of each data bit of the Data Bus increases. With the increase of the capacitive loading on the Data Bus, the driver of the data bit line is taxed for higher driving capability. As is well known, when the capacitive loading on a data line increases, the speed at which the corresponding driver circuit can change state on the data line decreases. Thus, on a given data line, the capacitive loading and the speed of data transfer are inversely proportional.
Many bus schemes have been designed to maximize speed in memory modules having increasing memory density. For that purpose, circuits utilizing pass gate switches have been designed into the data path to isolate and reduce the capacitive loading.
There are several factors to be considered in the design of such Bus circuits: 1) Data pulse widths in the nanosecond and sub nanosecond range limited by high frequency data rates.
2) Data bus width to satisfy wide Data Bus requirements of the CPU.
3) High Memory density on the same Data Bus (More Memory Modules attached to the same Data Bus, more connectors on the motherboard attached to the Bus.) 4) Presence of physical parameters of Resistance, Inductance and Capacitance (RLC) in the structure of the Data Bus and on the devices (Connectors, Memory modules, Printed circuit boards, Memory chips and logic chips connected to the Bus).
5) Effects of the physical RLC quantities affecting the overall speed by which data can be transported on the Bus and thus the overall performance and bandwidth of such Bus.
6) Synchronization of the Data signals and Strobe signals required to latch the data at the destination receiver.
Solutions to these problems in the prior art implemented systems having dual data banks, in which the data rate at each data bank is one-half the data rate at the system bus. However, further increases in computer speed have created synchronization problems in the reading and writing of data between the system bus and the memory banks.
The present invention presents a radical improvement over the prior art by generating strobe signals and data signals which are synchonized with each other at both the computer bus, which operates at twice the basic computer clock frequency where two data banks are used, and at the memory banks, which operate at the basis computer clock frequency.
Unlike the prior art, the present invention allows the Bus of data rate 2× frequency to be connected to device interface of 1× data rate frequency and vice versa.
The present invention provides a significant improvement in memory data rate speed and accuracy with substantial improvement in synchronization between the strobes and data in either direction of transmission and reception and better quality of signal over the prior art.